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Microchip Technology /ATSAMV71N20 /MCAN0 /FBTP

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Interpret as FBTP

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FSJW 0FTSEG2 0FTSEG10FBRP0 (DISABLED)TDC 0TDCO

TDC=DISABLED

Description

Fast Bit Timing and Prescaler Register

Fields

FSJW

Fast (Re) Synchronization Jump Width
FTSEG2

Fast Time Segment After Sample Point
FTSEG1

Fast Time Segment Before Sample Point
FBRP

Fast Baud Rate Prescaler
TDC

Transceiver Delay Compensation

0 (DISABLED): Transceiver Delay Compensation disabled.

1 (ENABLED): Transceiver Delay Compensation enabled.
TDCO

Transceiver Delay Compensation Offset

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data